# SMT-LIB 2.7 / AIGER / BTOR2 Formal Verification Orchestrator (CDCL + BMC + k-Induction + Craig Interpolation + IC3)

A complete in-browser formal-verification stack — no cvc5/Z3 binary needed: an SMT-LIB 2.7 script parser for the QF_BV + Bool core with Tseitin bit-blasting of the FixedSizeBitVectors operators (add/sub/mul/udiv/urem, shifts, comparators, concat/extract/extend, ite), an AIGER reader (ASCII aag and binary aig with delta decoding; outputs as bad properties), a BTOR2 reader with word-level bit-blasting, and a hand-written CDCL SAT engine (two-watched literals, VSIDS-style activities, 1-UIP learning, restarts) underneath. On sequential models it runs bounded model checking with counterexample-witness traces, k-induction with unique-state strengthening, McMillan-style Craig interpolation computed from the refutation and independently re-certified by SAT before being trusted, and an IC3/PDR-lite frame loop with predecessor-cube blocking.

> Canonical page: https://elysiatools.com/en/tools/smt-smtlib-2-7-cvc5-z3-btor2-aiger-k-induction-cddr-dbg-invariant-synthesis-orchestrator

- **Category:** Science & Education

- **Keywords:** smt-lib parser, qf_bv solver, cdcl sat engine, aiger reader, btor2 model checking, bounded model checking, k-induction invariant, craig interpolation, ic3 pdr lite, counterexample trace

## Overview

Everything runs on a self-contained TypeScript stack: the SMT-LIB front end covers the common QF_BV/Bool operator set (with define-fun inlining and let bindings), AIGER files are read in both ASCII and binary (delta-encoded ANDs, latch next functions, outputs interpreted as HWMCC bad signals), and BTOR2 models are bit-blasted from the word level (sorts, consts, states with init/next, bad/constraint/output, and the arithmetic/logic opcode core). The SAT core is a real CDCL solver — two-watched literals, clause learning with first-UIP backjumping, activity-based branching and restarts — the same algorithm family inside cvc5 and Z3, at didactic scale. Safety engines: BMC finds shortest counterexamples with full input/state traces; k-induction adds unique-state constraints to catch invariants that plain induction misses; the interpolation engine derives candidate Craig interpolants from the refutation structure and then re-verifies each candidate by independent SAT calls before calling it an invariant — an unverified candidate is never reported as one; and IC3-lite maintains per-frame blocked cubes with k-induction closing the proof. Scale guidance: bit-vector widths ≤ 16 and bounds ≤ 30 keep runs interactive.

## Inputs

- **Model source** (select)
- **Model text (when pasting)** (textarea): (set-logic QF_BV) (assert ...) (check-sat) | aag M I L O A ... | 1 sort bitvec 8 ...
- **Verification engine** (select)
- **Bound k for BMC / induction (1–30)** (number): 10

## When to use

- When checking safety invariants or unreachable error states in word-level BTOR2 and bit-level AIGER sequential circuit designs.
- When proving bit-vector equivalences, algebraic identities, or refuting negated specifications in SMT-LIB 2.7 QF_BV format.
- When synthesizing and validating inductive invariants using multiple complementary formal engines like k-induction, Craig interpolation, and IC3.

## How it works

- Parse SMT-LIB 2.7 QF_BV assertions, AIGER transition systems (ASCII or binary), or word-level BTOR2 models into internal representations.
- Perform Tseitin bit-blasting on fixed-size bit-vector operators, arithmetic logic, and transition relations to generate propositional clauses.
- Execute selected verification engines (BMC, k-induction, Craig interpolation, or IC3) on top of a native CDCL SAT solver using two-watched literals and 1-UIP learning.
- Output formal verdicts (sat/unsat/safe/unsafe), detailed SAT engine conflict metrics, and full step-by-step counterexample witness traces when safety properties fail.

## Use cases

- Hardware engineers verifying safety assertions, latch reachability, and bad-state conditions in AIGER and BTOR2 circuit netlists.
- Software verification researchers testing automated invariant synthesis algorithms and comparing engine performance across BMC, k-induction, and IC3.
- Students and educators analyzing CDCL solver statistics, bit-blasting structures, and refutation mechanics on bit-vector arithmetic.

## Frequently asked questions

### Do I need to install cvc5, Z3, or any local solver binaries?

No. The parser, bit-blaster, and CDCL SAT solver are entirely self-contained and run directly in your browser.

### Which input model formats are supported?

The tool supports SMT-LIB 2.7 (QF_BV and Bool logic), AIGER format (both ASCII .aag and binary .aig), and word-level BTOR2 models.

### What is the recommended size limit for responsive verification?

Bit-vector widths up to 16 bits and unrolling depths (bound k) up to 30 maintain smooth, interactive in-browser performance.

### How are Craig interpolant invariants validated?

Candidate interpolants extracted from refutation proofs are independently certified by additional SAT checks before being reported as invariants.

### What details are included in counterexample outputs?

When a safety property is violated, the report presents the precise step count, state variable values, and input trace across every unrolled step.

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