# PCIe Link Training LTSSM & Lane Margining Eye Decoder Decode a PCIe link training log (LTSSM state sequence plus TS1/TS2 ordered sets) into the full Gen1-Gen6 state timeline: negotiated speed and width, rate identifier bits, lane reversal, polarity inversion, equalization phases and Detect/Recovery restart diagnostics. Also grades a lane margining report (pcilmr CSV or key=value) against the PCIe Base Spec Rev 5.0 §8.4.2 eye minimums per generation and renders a per-lane eye-margin heatmap SVG. > Canonical page: https://elysiatools.com/en/tools/pcie-link-training-linkstate-and-lane-margining-eye-decode - **Category:** Network - **Keywords:** pcie, ltssm, link training, lane margining, eye diagram ## Overview Decode PCIe Link Training and Status State Machine (LTSSM) logs and lane margining reports into structured diagnostic summaries. This tool parses state sequences, TS1 and TS2 ordered sets, rate identifiers, and equalization phases across Gen1 through Gen6, while grading receiver eye margins from pcilmr CSV outputs against PCIe Base Specification thresholds with generated SVG heatmaps. ## Inputs - **LTSSM Log / Margining Report** (textarea): t=0.00ms Detect.Quiet t=0.90ms Polling.Active TS1 link=PAD lane=PAD rate=0x01 t=6.40ms Configuration.Lanenum.Accept TS1 link=0 lane=3 t=7.40ms L0 …or pcilmr CSV: Lane,EW Min,EW Rec,EW,… - **PCIe Generation (for margining)** (select) - **Render eye-margin heatmap (SVG)** (checkbox) ## When to use - When troubleshooting PCIe link training failures, down-training, or speed fallback loops across Detect, Polling, Configuration, and Recovery states. - When evaluating receiver eye-margin compliance and signal integrity using Linux pcilmr CSV or key-value data. - When inspecting equalization Phase 1 through Phase 3 progression, lane reversal, and polarity inversion during board bring-up. ## How it works - Paste raw LTSSM state sequences, TS1/TS2 ordered set traces, or pcilmr CSV output into the log text area. - Select the target PCIe generation or leave it on auto-detection to apply the relevant PCIe Base Specification §8.4.2 eye limits. - Optionally check the SVG heatmap option to generate visual per-lane eye-width and eye-height margin charts. - Inspect the decoded state timeline, negotiated speed and width badges, equalization diagnostics, and per-lane margin grades. ## Use cases - Link Bring-Up Analysis: Inspect high-speed negotiation and Phase 1 to Phase 3 equalization transitions on prototype boards. - Receiver Margin Qualification: Grade pcilmr margining results across all lanes to verify hardware compliance before production release. - Hardware Fault Isolation: Pinpoint whether link degradation stems from physical polarity issues, lane numbering mismatches, or Recovery timeouts. ## Frequently asked questions ### What input formats are supported by the decoder? The decoder accepts LTSSM state trace lines, TS1/TS2 ordered set strings, Linux pcilmr -o 22-column CSV data, and key-value margin lines. ### How is the PCIe generation determined for margining? It automatically infers the generation from the minimum eye width (EW Min) column or uses the manual Gen4, Gen5, or Gen6 dropdown selection. ### What standard is used to grade lane margins? Margins are graded as Perfect, Pass, or Fail against PCIe Base Specification Rev 5.0 §8.4.2 minimums and PHY Test Specification recommendations. ### Can the tool detect lane reversal and polarity inversion? Yes, it parses link and lane identifiers, PAD flags, and polarity inversion markers present in the TS1/TS2 ordered set records. ### Is data processed locally? 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